Description
Dual Positive-Edge-Triggered D Flip-Flops
Clear and Complementary Outputs
Specification:
| Operating Voltage Range | 4.5 V to 5.5 V |
| Package | DIP−14 |
| Input Current | 1 mA |
| Powering Current | 15 mA |
| Propagation Delay | 25 ns |
| Temperature Range | -65 °C – 150 °C |
Pin Configuration:
| Input (1D, 2D) | 2, 12 |
| Inverting Output (1Q’, 2Q’) | 6, 8 |
| Non-Inverting (1Q, 2Q) | 5, 9 |
| Clock (1CLK, 2CLK) | 3, 11 |
| Enable Pin (ENP, ENT) | 7, 10 |
| Preset (1PRE’, 2PRE’) | 4, 10 |
| Power Supply (VCC) | 16 |
| Ground (GND) | 8 |
This device contains two independent positive-edge-triggered D flip-flops with complementary outputs. The information on the D input is accepted by the flip-flops on the positive going edge of the clock pulse. The triggering occurs at a voltage level and is not directly related to the transition time of the rising edge of the clock. The data on the D input may be changed while the clock is LOW or HIGH without affecting the outputs as long as the data setup and hold times are not violated. A low logic level on the preset or clear inputs will set or reset the outputs regardless of the logic levels of the other inputs.
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