74112 Dual J-K Flip-Flop IC – Negative Edge-Triggered Logic Chip

Description

• Dual JK Negative Edge Triggered Flip-Flops With Preset and Clear
• High-level input voltage: 2V
• Low-level input voltage: 0.8V
• High-level output current: -0.4mA
• Low-level output current: 8mA
• Maximum clock frequency: 45MHz
• Propagation delay time: 20ns
• Supply voltage range: 4.75 to 5.25V
• Package: DIP-16

The SN74LS112AN is a dual J-K Negative-Edge-Triggered Flip-Flop with clear and preset. When preset and clear are inactive (high), data at the J and K inputs meeting the setup time requirements are transferred to the outputs on the negative-going edge of the clock pulse. Clock triggering occurs at a voltage level and is not directly related to the rise time of the clock pulse. Following the hold time interval, data at the J and K inputs may be changed without affecting the levels at the outputs. This versatile flip-flop can perform as toggle flip-flop by tying J and K high. The SN74S112A is characterized for operation from 0 to 70°C.

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